Division circuit



Sept 20, 1966 NOBORU AMANO ETAL 3,274,381

DIVISION CRCUIT Filed sept. 11, 1962 xlG---l Pfg! Output volacge 62 in Volt,

| l lo" m"f xo 3 m InPu current il n ampere.

Fi 2 NVENTORS Noboru Amano 8\ Nooclk Wukoyomo BY Ww ATT NEY United States Patent Oiice 3,274,381 Patented Sept. 20, 1966 Japan Filed Sept. 11, 1962, Ser. No. 222,834 Claims priority, application Japan, Nov. 18, 1961, 36/41,655 Claims. (Cl. 23S-196) This invention relates to a division circuit and more particularly, relates to Ia division circuit in which an alternating current modulated by a -current or a voltage proportional to a dividend and a current proportional to a divisor are simultaneously introduced into a logarithmic element and only the com-ponent of the A.C. fundamental wave among the voltage appearing across the both ends of said logarithmic element is picked up, amplied and demodulated.

It is lan object of this invention to provide a division circuit in which the divisional operation of an analogue quantity is effected with speed and accuracy by means of a simple construction.

The nature of the invention as well as other objects and advantages thereof will become apparent from considera tion of the 4following specification and relating to the annexed drawing, in which FIGURE 1 is a block diagram of a division circuit of the invention.

FIGURE 2 is a graphical plot showing the relationship among the input currents Xand output voltage of the division circuit of FIGURE 1.

In FIG. l, terminal 1 is an input terminal `for a D C. current the magnitude of which 4is proportional to divisor A, terminal 2 is an input terminal for an A.C. current i2 `sin ntl the amplitude of which is proportional to a dividend B. Terminal 3 is a common input terminal `for these currents. The voltage across logarithmic element i4, is a linear function of the logarithm of the current through the element.

Filter amplifier `5 is a tuned amplifier of which the tuned `frequency is w, and the input impedance of this amplier is quite large compared with the dynamic im pedance of the logarithmic element 4, Terminals 6 and 7 are output terminals for an AJC. signal whose ampliture is proportional to a quo-tient 1'2/1'1 or B/A. When the input current corresponding to the dividend B lis D.C., Idevices which are shown by broken lines in FIG. 1 are used. Terminal 11 is an input terminal ffor the D.C. current whose magnitude is proportional to the dividend B. Carrier oscillator 12 is a device to generate I0 sin wl. `Modulator l13 is a device t-o obtain i2 sin wt with the suppressed-carriermodulation.

The operation of the division circuit of this invention shown in FIG. 1 is as follows:

A D.C. current i1 whose magnitude is proportional to a divisor A enters from terminal 1 and an AlC. current i2 sin wt whose amplitude i2 is proportional to a divident B enters from Iterminal 2 and these currents return to terminal 3 through the logarithmic element 4. In this case, i1 must be yarranged to `be at least several times larger than i2, and angular 'frequency w is arranged to 'be qui-te large compared with the angular frequency of the variation of il and i2, A voltage e1 occurring across the logarithmic element `4 is represented as follows:

where: a and b are constants for a Igiv'en logarithmic element.

The voltage el is ampliied by the filter ampliiier 5, which has a tuned angular `frequency w, and only the signal components which have the angular frequency w are amplied and the others are rejected. A output voltage e2 of the lter amplier -5, which is also the voltage `between terminal 6 and terminal 7, is calculated by picking up and adding up terms containing sin wt in Eq. 1 and multiplying this sum by the voltage gain of the amplifer 5. There-fore, e2 is represented as follows:

eeen i where: C is the voltage gain of the filter amplier 5 for signals with the angular frequency w and D=A C.

lf the current i1 is arranged to be sufficiently large compared with i2, the magnitude of higher order terms are negligible compared with that of the irst term.

In such a case, it follows:

Thus the amplitude of the output A.C. voltage e2 between terminal 6 and terminal 7 is proportional to the quotient of i2 divided by 1'1 and, therefore, proportional to B/A.

The `theoretical relative error Er of this division circuits, which occurs when the current i1 is arranged not to 'be suiiiciently large compared with i2, is as follows:

Z1 1 i2 2 1 1'2 4 "4 +8 L 4) and in fact, when the ratio of i2 to i1 is 1/ 10, the relative error is about 0.3%.

With regard to a waveform of the output signal corresponding to the quotient, when it is required to be D,C., the output `signal e2 of the -lter ampliier is demodulated by the demodulator 8, and when z', is arranged to be sufciently large compared with i2, an output voltage of the demodulator 48 or a voltage e3 between terminal l9 and terminal 10 -is as follows:

:Go2/geehrt (5) where: F is the voltage elficency of the demodulator and G=DF Thus the DiC. voltage whose magnitude is proportional to the quotient B/A is obtained between terminal 9 and terminal 10.

In the abovementioned circuit, the input current corresponding to `the divisor A is D.C. and dividend B is A C.

When the :input current corresponding to the dividend B is also D.C., it is necessary to convert the D.C. current into an A.C. current whose amplitude is proportional to the magnitude of the D.C. current.

In such a case, devices which are shown by broken lines lare used.

The operation of these devices is as follows:

Carrier oscillator 12 generate a signal, an angular frequency of which is w, and the output current I sin wt of this oscillator 12 is modulated by the input current i2, corresponding to the dividend B and coming in through terminal 11, by means of the suppressed-carrier-rnodulation. Consequently, the output current of modulator 13 is i2 sin wt. This signal is introduced to said terminal 2 and the divisi-on is carried out .with said operation.

As will be understood from the above description, lwhen the dividend is a constant it is sufficient that the output current of modulator 13 `be a constant amplitude. Thus, the current applied t-o the logarithmic element 4 will be a summation of the current il and the current i2 sin wt, the current i1 corresponding to the divisor and the current i2 sin wt corresponding to the dividend and being of a constant amplitude.

It should be understood that the embodiment herewith shown and described is the form 'of the inventi-on at present preferred, but the scope of the invention is not limited to the precise details of Aformulation herein shown but -is to be ascertained by reference to the aippended claims.

What is claimed 'ist 1. A division circuit comprising means to introduce lan alternating current proportional to a dividend and `a current proportional to 'a divisor simultaneously into a logarithmic element, the voltage across said element being proportional t-o the logarithm of the current flowing through said element, means to pass only the component of the A.C. fundamental wave from the voltage yappearing across said element, and means to amplify and to demodulate said component.

2. A division circuit as in claim 1 further comprising means to produce said alternating current suppressedcarrier-modulated by a current or said voltage proportional to a dividend.

3. A division circuit `as in claim '1 wherein said alternating current -is of constant amplitude.

4. A division circuit for the production of a signal of a magnitude proportional to a quotient of the magnitude -of two input signals, comprising a logarithmic element, means of simultaneously introducing into said element `an A.C. current having an amplitude proportional to a dividend and a -D.C. current having a magnitude proportional to a divisor, means to produce across said element a voltage which is a linear function of the logarithm of the current owing through said element and a Ililter amplifier f-or amplification of only that frequency component of the voltage occurring across said element, rwhich is at the fundamental frequency of the A.C. current representing the dividend.

5. A division circuit as claimed `in claim 4, further comprising means of demodulating the output signal.

References Cited by the Examiner UNITED STATES PATENTS 2,700,135 1/1955 Tolles 23S-194 2,861,182 11/1958 Green 235-197 3,092,720 6/1963 ADeVrijer 23S-196 3,162,758 12/1964 Kamen 23S-196 OTHER REFERENCES Ives Direct Recording of Wind Slip, Journal of the Franklin Institute, vol. 270, No. 3, September 1960, pages l7l-172.

Kahn, Herbert L. Multiplication and Division Using Silicon Diodes, Review of Scientic Instruments, volume 33, No. 2, February 1962, pages 23S-237.

ROBERT C. BAILEY, Primary Examiner.

MALCOLM A. MORRISON, Examiner.

G. D. SHAW, Assistant Examiner. 

1. A DIVISION CIRCUIT COMPRISING MEANS TO INTRODUCE AN ALTERNATING CURRENT PROPORTIONAL TO A DIVIDEND AND A CURRENT PROPORTIONAL TO A DIVISOR SIMULTANEOUSLY INTO A LOGARITHMIC ELEMENT, THE VOLTAGE ACROSS SAID ELEMENT BEING PROPORTIONAL TO THE LOGARITHM OF THE CURRENT FLOWING THROUGH SAID ELEMENT, MEANS TO PASS ONLY THE COMPONENT OF THE A.C. FUNDAMENTAL WAVE FROM THE VOLTAGE 